1. Field of the Invention
The present invention relates to a system and method for polishing semiconductor wafers and, more particularly, to the polishing of damascene formed interconnects on the wafer using the chemical-mechanical polishing process in order to achieve a high degree of damascene planarity.
2. Description of Related Art
In the fabrication of integrated circuit devices, numerous integrated circuits are typically constructed simultaneously on a single semiconductor wafer. The wafer is then later divided by cutting the wafer into the individual integrated circuit devices.
Typically, the integrated circuit device is made by a series of layering processes in which metallization, dielectrics, and other materials are applied to the surface of the wafer to form a layered interconnected structure. One important step in the fabrication process is to form interconnects in the insulator layers. The interconnects connect different layers of the integrated circuit device together and provides an integrated circuit device having high complexity and circuit density.
One method for forming the interconnects is to use a damascene method wherein, in general, a via or trench pattern is etched into a planar dielectric layer and then the pattern is filled by metal. Excess metal is typically applied and covers the upper surface of dielectric. The excess metal is then polished away to the patterned metal surface. As with other steps in the fabrication process, it is of extreme importance that the polished interconnect damascene layer be planar.
In order to achieve the degree of planarity required to produce ultra high density integrated circuits, chemical-mechanical planarization processes are now typically employed in the industry. In general, the chemical-mechanical planarization (CMP) process involves pressing a semiconductor wafer against a moving polishing surface that is wetted with a chemically reactive, abrasive slurry. Slurries are usually either basic, acidic or neutral and generally contain alumina or silica particles. The polishing surfaces typically are a planar pad made of a relatively soft, porous material such as blown polyurethane. The pad is usually mounted on a planar platen.
In the CMP process, the wafer is typically secured to a carrier plate by vacuum or by a mounting medium such as an adhesive with the wafer having a force load applied thereto through the carrier by a pressure plate so as to press the wafer into frictional contact with the polishing pad mounted on a rotating turntable. The carrier and pressure plate also rotate as a result of either the driving friction from the turntable or rotational drive means directly attached to the pressure plate. In a typical polishing machine, the wafer is transported across the polishing surface to polish the wafer. The CMP process is well known and U.S. Pat. No. 5,423,716 is exemplary and the disclosure of the patent is hereby incorporated by reference.
With regard to the semiconductor devices formed from the wafer, the devices typically include a plurality of interlayered circuits such as metal lines forming an integrated circuit which are interconnected by vias or interconnects between the layers. In the damascene process, metallization of the interconnects is performed by etching the desired circuitry in the dielectric layer down to the active region of the device. A thin layer of conductive metal is deposited by, for example, vacuum evaporation, sputtering or chemical vapor deposition (CVD) techniques, over the entire wafer. The unwanted portions of this metal layer are removed by CMP leaving the thin lines of metals as interconnects.
Both single damascene structures and double damascene layers may be made by the same process and both processes require a CMP process to polish the wafer down to the surface of the interconnects and provide a planar surface. Unfortunately, problems such as dishing occur causing a non-planar surface. The dishing effect is particularly serious since the polishing needs to be carried out until the metal is cleared on the entire wafer, i.e., wherein the metal is left exclusively in previously etched lines without any metal on the surface of the dielectric. It has been found that a significant overpolish is typically needed which results in erosion of dielectric and dishing of metal as much as 100 nm below the level of the dielectric surface. As a consequence, the thickness of the interconnects in overpolished areas is severely reduced resulting in an increased sheet resistance as compared to interconnects in other areas of the wafer and/or the individual integrated circuit device. Additionally, an uneven topography is introduced on the wafer surface after CMP which will be repeated with slight attenuation after subsequent deposition of dielectric layers problems at later steps in the fabrication process.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for polishing semiconductor wafers and other workpieces which have been coated with a layer of metal in a damascene process.
It is an additional object of the invention to provide an apparatus for polishing semiconductor wafers and other workpieces during the damascene step of the fabrication process.
It is another object of the present invention to provide planar workpieces, including semiconductor wafers, made using the improved method and apparatus of the invention.
Other objects and advantages of the present invention will be readily apparent from the following description.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed, in a first aspect, to a method for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer comprising the steps of:
preferably dividing each chip on the wafer into a plurality of regions;
determining the metal density for each region of each chip based on the circuit pattern for that region;
adding a dummy circuit pattern to each region on each chip to provide at least a minimum metal density in each region or setting a maximum and/or minimum metal density for each region;
forming both the desired circuit pattern and any dummy circuit pattern as openings in a dielectric layer on each chip;
coating the patterned dielectric layer with a layer of metal which metal fills the openings forming the desired circuit pattern and any dummy circuit pattern and covers the surface of the wafer including the circuit patterns; and
polishing the metal coated wafer until no metal remains outside the desired and any dummy circuit patterns.
Broadly stated, the invention is directed to providing a uniform distribution of damascene metal line circuitry across each integrated circuit chip. For a typical integrated circuit chip, the pattern factor of metal circuitry on a damascene layer varies up to about 80 or 90% and the pattern factor for a particular area or region may be defined as the area covered by the metal divided by the total area of the particular area or region. Thus, if in a square area bounded by sides of 20 microns by 20 microns, the metal covers an area of 200 square microns, the pattern factor is 50%.
In areas of high pattern factor (HPF), e.g., 60% it has been found that the metal surface, after deposition, is lower than in areas of low pattern factor (LPF) areas, e.g., 20% due to mass conservation during the sputtering or other deposition process. As a consequence, during the CMP process, the metal above the dielectric is removed differently in HPF areas as compared to LPF areas. Since the polishing needs to be carried out until the patterned metal is cleared on the entire wafer leaving metal exclusively in previously etched lines, HPF areas generally experience a significant overpolish resulting in erosion of the dielectric and dishing of metal up to 100 nm below the level of the dielectric surface. As a result, the thickness or height of lines (interconnects) in HPF areas is thinner or shorter resulting in increased sheet resistance as compared to the thicker lines in LPF areas.
To overcome the dishing effect and other non-planarization, the invention decreases the differences in pattern factors for regions on the chip. For example, for HPF areas of up to 90% as compared to LPF areas of 0% or 20-30%, the difference in pattern factor may be as high as 90%. It is one aspect of the invention to decrease the difference in pattern factor across the chip surface by providing a uniform metal density (pattern factor) across the surface of the chip and, concomitantly, of the wafer.
In another aspect of the invention, a method is provided to set a predetermined high pattern factor design limit of say 60-90%, preferably 70-80%. Using this method, the difference between the high pattern factor areas and the low pattern factor areas is minimized due to the lower upper design limit of the HPF areas.
In a further aspect of the invention, a predetermined low pattern factor design limit is set. For a lower limit of, for example, 20-50%, differences between the high and low pattern factors on the chip are minimized.
In a preferred aspect of the invention, a high pattern factor design limit and a low pattern factor design limit are both defined which will result in increased metal circuitry uniformity across the chip and wafer surface. For example, if the HPF limit is set at a maximum of 70% to 80% and a LPF limit at a minimum of 40% to 50%, the circuit density of the areas will differ by only 20% to 40% across the surface of the chip and wafer and result in a metal surface which has significantly less erosion or dishing after CMP processing.
In another aspect of the invention, the lower pattern factor design limit can be artificially generated for any given region on the chip or wafer surface by using a dummy circuit design. While it is preferred that an upper pattern factor limit also be used, this is not necessary and the use of a dummy circuit pattern layout will minimize the difference in circuit density over the chip and wafer surface and provide for a uniform metal surface after CMP.
Basically, the data defining the metal features on a given damascene level would be inputted into a computer and an algorithm used to generate dummy circuitry to increase the circuitry to at least a lower pattern factor limit for a particular region. While the types and sizes of the circuitry can be chosen in a wide range, it is preferred to generate circuitry features of uncritical size like 1 micron wide lines with 1 micron spacing. More preferred is to mimic the size of the chip circuitry.
It is an important feature of the invention that the dummy lines do not have any electrical contact to features of the chip design. Ideally, the dummy lines are connected through underline (or above line) levels to the substrate to avoid floating capacitances in the neighborhood of current leading wires acting as a parasitic noise and RC delay source.
In a further aspect of the invention, the method of the invention is also directed to the control of the metal density (pattern factor) over the entire wafer. This is important since there are areas at the periphery of the wafer which are not formed into chips because of the curved configuration of the wafer but may still effect the metal uniformity of the wafer and may result in dishing after the CMP process. It is therefore an additional feature of the invention to form partial dummy chips (with metallization) out to the edge of the wafer so that the entire wafer is covered with chips and chip fragments of a more uniform metal pattern factor.
In a further aspect of the invention, an apparatus is provided to make planar damascene wafers. Wafers made using the apparatus and method of the invention are also contemplated herein.
An apparatus for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer comprises:
a rotatable turntable assembly;
a polishing pad supported on said assembly;
a rotatable carrier located above said assembly and adapted to hold a silicon wafer during planarizing and positioned between said carrier and said polishing pad; and
means for changing the pattern factor (metal density) of metal across the surface of the wafer (preferably region by region) by either setting a high metal density pattern factor design limit and/or a low metal density pattern factor design limit or by using a dummy circuit design on the wafer surface.